Design of integrated circuits to perform newly identified functions has progressed for many years. Presently, system level designers who determine a need for a newly defined integrated circuit, for example to integrate a variety of functions into one chip, use two primary approaches. In the first known approach, a field programmable gate array (FPGA) is used. In the second known approach, application specific integrated circuit (ASIC) design is used. Each of these prior art approaches has disadvantages which are described in detail below.
FIG. 1 depicts a block diagram view of an application specific integrated circuit (ASIC) or “system on a chip” (SOC) design 100 that may be obtained using current cell based design approaches (CBD). In FIG. 1, an embedded functional module 101, which is a known function such as a microprocessor, RISC processor, analog to digital converter, radio transceiver such as for a mobile telephone or wireless device, or other known function such as a memory module, is incorporated with a plurality of user defined logic units. Another function 102 is also shown, which could be for example embedded memory. Logic cells 104 are shown disposed in rows in partition blocks 105. Routing channels 106 provide connections between the various blocks and logic cells.
FIG. 2 depicts a prior art design flow for performing integrated circuit design using a prior art CBD approach. The steps of FIG. 2 may be performed using electronic design automation (EDA) tools that are commercially available. In the first step, 211, a system design step is performed. System design may be performed using various tools that are commercially available, such as hardware description language (HDL) and VHDL descriptions, known functions may be available as reusable modules licensed by vendors such as processor and DSP modules and referred to as “IP”, or callable routines, software modeling may be done in various environments. Typically system design is performed using high level descriptive constructs and simulations are then performed using the EDA tools to verify that the function specified by the behavioral HDL or VHDL model is correct. That is, the simulation verifies the design model in fact gives the right outputs for a given set of inputs or conditions, and that the design described will meet the overall functional requirements. In some cases multiple integrated circuits may be defined in a single system model, in other cases a specific integrated circuit may be defined.
Once the system definition for an integrated circuit is completed, the design flow transitions to a logic synthesis step 213. In automated logic synthesis, the behavioral model is replaced by a functionally equivalent register transistor level (RTL) or logic based model based on certain known functions by EDA synthesis tools. For example, selections between variables in the VHDL model may be replaced by a multiplexer RTL description; storage statements in the VHDL model may be replaced by RTL descriptions of registers or latches, delays may be replaced by delay lines, “add” statements may be replaced by an adder RTL representation, and so forth. The logic synthesis process results in a second description of the device which may then be verified functionally by another simulation and test process, typically using test patterns obtained in the simulations at the system design step.
After the logic synthesis 213 is complete, the device may be described as a netlist of logical functions that are technology independent. The functions may include register transfer language (RTL) or similar register and logic level descriptions including elements such as descriptions of adders, registers, multiplexers and the like. EDIF or other output formats may be provided for the logical level netlist.
Once the technology independent logic model for the cell based design is complete, the technology independent logic level description is again transformed, through the use of standard cell libraries and using technology mapping tools, to a netlist model of technology dependent standard cell or functional modules for known functions. The standard cell approach replaces technology dependent gate level models for the technology independent logical models. Gate loading, drive strength, and other specific parameters that vary with process technology may be considered in making the technology mapping. The new netlist is populated with the proper circuits from a standard cell library to implement the circuit desired in a specific semiconductor process. Once again a verification process is needed to verify that the technology dependent gate level netlist and the cells and connections used in the gate level model fact are functionally equivalent to the behavioral model.
After the standard cell library is mapped onto the design, the automated design tools can place the elements of the circuit in a proposed circuit placement. A circuit designer may assist with placement based on certain parameters or design needs that the designer is aware of, for example a memory might be placed adjacent the outside of the integrated circuit to make it physically proximate to an external data buss. Alternatively, automatic placement tools may be used as are known in the art.
After placement is complete, the circuit layout process can continue. First the global routing is performed at step 217. Automated route tools are executed which, using known cost functions based on the length of conductors, number of interconnects, resistance, power and metal migration requirements, and the pre-positioned routing channels provided by the placement tools, the major routing signals are placed, for example power, ground, clock and similar nets are routed in the global route step.
Following the global routing step, additional routing steps 227 and 219 are used to interconnect blocks as specified by the netlist, and detail routing of certain standard cell functions is performed. Following these steps a layout level model of the design is complete. Physical verification step 221 is performed to verify that the transistors and conductors specified are correctly coupled, and that no shorts or opens are formed.
The standard cell design flow ends at step 223 with a Graphic Data Systems II (GDSII) database. The GDSII output specifies graphical data describing the layout of the integrated circuit including the shapes for the transistors, the conductors, and the vias and contacts, etc. The GDSII output is formatted in terms of the individual layers and this data is needed to generate the photomasks to be used. The photomasks are used in a photolithographic semiconductor fabrication process to fabricate a wafer with a plurality of the circuit devices formed upon it. A set of masks for a new SOC may cost over 500,000 dollars to produce. The integrated circuit must then be manufactured from the set of masks in a semiconductor processing facility. Following manufacture of the silicon wafers, tests are run to verify the devices operate, the individual devices may be separated by a singulation step, additional tests performed, and integrated circuit packaging, and additional testing of the individual integrated circuits are needed before the completed circuit is available to the customer. This cell based design process of the prior art thus requires expensive non-recurring manufacturing costs for the masks, package design, test pattern generation, and a lengthy turnaround time to get the first ICs completed for system verification.
Standard cell design manufacturing of SOCs or ASICs in the prior art is known to have several disadvantages. The need for a unique set of photomasks for each new IC defined incurs a substantial start up or non recurring engineering (NRE) cost. The use of random placements and routing results in circuit designs that may exhibit very wide process variation sensitivities. The time for producing the first integrated circuits may be very long. The engineering skills needed to design in the cell based design flow may not be present at all companies, as many different EDA tools are used and experience with system level, gate level, physical level integrated circuit layout and physical level design requirements such as packaging is necessary.
FIG. 3 depicts in a block diagram an integrated circuit 200 designed using an FPGA approach. Unlike the SOC CDB approach, for the FPGA approach a completed integrated circuit is provided as base material. The FPGA is configured with existing programmable logic functions and programmable interconnections. Automated design tools are then used to implement the customer design by mapping the design into the FPGA resources and to complete the process by programming functions and interconnections inside the FPGA device. Programmation may be accomplished by metal fuses, via programmation, non-volatile memory cells, or other means. At the end of the programming step a completed integrated circuit is immediately available for use; no additional manufacturing time is required.
In FIG. 3 FPGA 200 is depicted. Functional module 201 may be a known complete IP function such as a processor, DSP, or embedded memory module which the FPGA manufacturer has provided. Routing channels 204 are provided with routing conductors already formed in a manner that allows connections between them to be made by interconnect programmation. Logic units 203 are provided in a predefined placement. Logic units 203 may include clocked circuits such as registers, storage elements and the like, as well as configurable logical blocks and other known functions such as multiplexers and buffers. Many rows of the logic units are provided. Initially the functions of these logic units and the connections of these units are somewhat open. Simple EDA tools are used to create a programmation for the device and the tools are relatively inexpensive.
FIG. 4 depicts an example prior art design flow for designing an integrated circuit using an FPGA approach. Some of the steps in this top down design flow are similar to those in the CBD approach.
System design steps and logic synthesis steps 211 and 213 are similar to those described above and so will not be further described. After a technology independent circuit netlist is obtained, technology mapping step 231 is performed to create a netlist for implementing the design on the target FPGA. The FPGA is already a complete manufactured and packaged integrated circuit, except that the programmable functions and interconnections are yet to be formed, so the technology mapping step must use the available resources on the FPGA to implement the functions in the netlist, and once those are used no more are available. Thus the EDA tools used may be aware of the resources available in a particular FPGA being used, which is provided by an FPGA definition tool 245.
The global routing step 233 is different from the global routing in the standard cell design flow. The routing conductors are already physically placed as the FPGA is a completed integrated circuit. Only the connections need be completed. Detail routing step 235 for the FPGA design flow does not actually route the conductors, but instead determines which conductors are to be interconnected. Several approaches are known for programming FPGAs. In one anti-fuses or fuses are blown to form connections. In another via programming is used to complete vertical connections between conductors formed overlying one another in different layers. In any case the completed netlist is again subjected to a physical verification step in 237 to ensure proper connections are formed. Finally a programmation tool forms the completed netlist into the silicon device by programming an FPGA. In this design flow the end step results in a functional integrated circuit without the need for additional manufacturing steps. The time to get the integrated circuit manufactured and tested is thus saved over the ASIC flow. However, each FPGA circuit must be programmed individually to produce the final design using an appropriate FPGA programming device.
Each of these prior art approaches to designing and producing a new integrated circuit has several disadvantages. Because FPGA devices are supplied as a completed IC with a variety of functions already implemented, and because the programmation blocks require additional circuitry, the devices are very expensive on a per unit basis and are therefore only economically useful at low volumes. Typically FPGA devices are not available at the most advanced technology nodes, for example current FPGA devices are available at the 90 nanometer technology node, while advances in semiconductor processing have moved to 60, 45, and now 32 and 28 nanometer technologies which offer smaller transistors, higher performance and lower power requirements, these advantages are not available to FPGA designers.
The prior art CBD approach has advantages over the FPGA approach in that it provides more flexibility in circuit design, allows access to more advanced semiconductor processes, and has a lower per unit cost in the long term and therefore is more useful for higher volumes. However the CBD SOC or ASIC approach requires substantial additional expense to create a unique mask set, the cost to manufacture silicon wafers, test pattern development, as well as time and expense for performing packaging and additional tests that are required, and therefore the CBD approach incurs a lengthy delay to get the completed devices. These SOC devices are also known to have great sensitivity to process variations. Further SOC design requires additional design skills to perform that the customer may have to either hire, or purchase from another vendor, adding additional costs. Many companies simply do not have the resources to use this approach.
A continuing need thus exists for a cost effective customer specified integrated circuit design and production, and methods that overcome the disadvantages of the prior art.